`include "../include/cpu_defines.sv"

module RATDIS_reg(
	input logic cpu_clk,
	input logic stall,
	input logic clear,
	input logic rat_inst1_en,
	input logic rat_inst2_en,
	input logic [5: 0] rat_inst1_origin_rs,
	input logic [5: 0] rat_inst2_origin_rs,
	input logic [5: 0] rat_inst1_rs,
	input logic [5: 0] rat_inst1_rt,
	input logic [5: 0] rat_inst2_rs,
	input logic [5: 0] rat_inst2_rt,
	input logic [5: 0] rat_inst1_rd,
	input logic [5: 0] rat_inst2_rd,
	input logic [31: 0] rat_inst1_src1,
	input logic [31: 0] rat_inst1_src2,
	input logic [31: 0] rat_inst2_src1,
	input logic [31: 0] rat_inst2_src2,
	input logic [5: 0] rat_rob_index1,
	input logic [5: 0] rat_rob_index2,
	input logic rat_rob_direction1,
	input logic rat_rob_direction2,
	input logic [`INST_TYPE_BUS] rat_inst1_type,
	input logic [`ALUOP_BUS] rat_inst1_aluop,
	input logic [`INST_TYPE_BUS] rat_inst2_type,
	input logic [`ALUOP_BUS] rat_inst2_aluop,
	input logic [`MEMOP_BUS] rat_inst1_memop,
	input logic [`MEMOP_BUS] rat_inst2_memop,
	input logic [`EXC_CODE_BUS] rat_inst1_exccode,
	input logic [`EXC_CODE_BUS] rat_inst2_exccode,
	input logic [`CP0OP_BUS]rat_inst1_cp0op,
	input logic [`CP0OP_BUS]rat_inst2_cp0op,
	input logic [`MULTOP_BUS] rat_inst1_multop,
	input logic [`MULTOP_BUS] rat_inst2_multop,

	`ifdef CPU_DEBUG
		input logic [31:0] debug_ratdis_inst1_in,
		input logic [31:0] debug_ratdis_inst2_in,
		output logic [31:0] debug_ratdis_inst1_out,
		output logic [31:0] debug_ratdis_inst2_out,
	`endif

	output logic dis_inst1_en,
	output logic dis_inst2_en,
	output logic [5: 0] dis_inst1_origin_rs,
	output logic [5: 0] dis_inst2_origin_rs,
	output logic [5: 0] dis_inst1_rs,
	output logic [5: 0] dis_inst1_rt,
	output logic [5: 0] dis_inst2_rs,
	output logic [5: 0] dis_inst2_rt,
	output logic [5: 0] dis_inst1_rd,
	output logic [5: 0] dis_inst2_rd,
	output logic [5: 0] dis_rob_index1,
	output logic [5: 0] dis_rob_index2,
	output logic dis_rob_direction1,
	output logic dis_rob_direction2,
	output logic [31: 0] dis_inst1_src1,
	output logic [31: 0] dis_inst1_src2,
	output logic [31: 0] dis_inst2_src1,
	output logic [31: 0] dis_inst2_src2,
	output logic [`INST_TYPE_BUS] dis_inst1_type,
	output logic [`ALUOP_BUS] dis_inst1_aluop,
	output logic [`INST_TYPE_BUS] dis_inst2_type,
	output logic [`ALUOP_BUS] dis_inst2_aluop,
	output logic [`MEMOP_BUS] dis_inst1_memop,
	output logic [`MEMOP_BUS] dis_inst2_memop,
	output logic [`EXC_CODE_BUS] dis_inst1_exccode,
	output logic [`EXC_CODE_BUS] dis_inst2_exccode,
	output logic [`CP0OP_BUS]dis_inst1_cp0op,
	output logic [`CP0OP_BUS]dis_inst2_cp0op,
	output logic [`MULTOP_BUS] dis_inst1_multop,
	output logic [`MULTOP_BUS] dis_inst2_multop
);

	always_ff @(posedge cpu_clk)begin
		if(clear)begin
			dis_inst1_en <= 0;
			dis_inst2_en <= 0;
			dis_inst1_origin_rs <= 0;
			dis_inst2_origin_rs <= 0;
			dis_inst1_rs <= 0;
			dis_inst1_rt <= 0;
			dis_inst1_rd <= 0;
			dis_inst2_rs <= 0;
			dis_inst2_rt <= 0;
			dis_inst2_rd <= 0;
			dis_rob_index1 <= 0;
			dis_rob_index2 <= 0;
			dis_inst1_src1 <= 0;
			dis_inst2_src1 <= 0;
			dis_inst1_src2 <= 0;
			dis_inst2_src2 <= 0;
			dis_inst1_type <= 0;
			dis_inst1_aluop <= 0;
			dis_inst2_type <= 0;
			dis_inst2_aluop <= 0;
			dis_rob_direction1 <= 0;
			dis_rob_direction2 <= 0;
			dis_inst1_memop <= 0;
			dis_inst2_memop <= 0;
			dis_inst1_exccode <= `EXC_NONE;
			dis_inst2_exccode <= `EXC_NONE;
			dis_inst1_cp0op <= 0;
			dis_inst2_cp0op <= 0;
			dis_inst1_multop <= 0;
			dis_inst2_multop <= 0;
			`ifdef CPU_DEBUG
				debug_ratdis_inst1_out <= 0;
				debug_ratdis_inst2_out <= 0;
			`endif
		end
		else if(~stall)begin
			dis_inst1_en <= rat_inst1_en;
			dis_inst2_en <= rat_inst2_en;
			dis_inst1_origin_rs <= rat_inst1_origin_rs;
			dis_inst2_origin_rs <= rat_inst2_origin_rs;
			dis_inst1_rs <= rat_inst1_rs;
			dis_inst1_rt <= rat_inst1_rt;
			dis_inst1_rd <= rat_inst1_rd;
			dis_inst2_rs <= rat_inst2_rs;
			dis_inst2_rt <= rat_inst2_rt;
			dis_inst2_rd <= rat_inst2_rd;
			dis_rob_index1 <= rat_rob_index1;
			dis_rob_index2 <= rat_rob_index2;
			dis_rob_direction1 <= rat_rob_direction1;
			dis_rob_direction2 <= rat_rob_direction2; 
			dis_inst1_src1 <= rat_inst1_src1;
			dis_inst1_src2 <= rat_inst1_src2;
			dis_inst2_src1 <= rat_inst2_src1;
			dis_inst2_src2 <= rat_inst2_src2;
			dis_inst1_type <= rat_inst1_type;
			dis_inst1_aluop <= rat_inst1_aluop;
			dis_inst2_type <= rat_inst2_type;
			dis_inst2_aluop <= rat_inst2_aluop;
			dis_inst1_memop <= rat_inst1_memop;
			dis_inst2_memop <= rat_inst2_memop;
			dis_inst1_exccode <= rat_inst1_exccode;
			dis_inst2_exccode <= rat_inst2_exccode;
			dis_inst1_cp0op <= rat_inst1_cp0op;
			dis_inst2_cp0op <= rat_inst2_cp0op;
			dis_inst1_multop <= rat_inst1_multop;
			dis_inst2_multop <= rat_inst2_multop;
			`ifdef CPU_DEBUG
				debug_ratdis_inst1_out <= debug_ratdis_inst1_in;
				debug_ratdis_inst2_out <= debug_ratdis_inst2_in;
			`endif
		end
	end

endmodule